WPR.C - Flexible Radio Platforms

Objectives

Flexibility is a sought-after and interesting property of radio systems, broadly required in current and (increasingly) forthcoming systems. It is expected to be a must in transceivers that will have to cope with more and more air interfaces and radio technologies in the future. Hence, flexibility is a means to achieve real-time processing in various radio environments with limited transceiver complexity and reasonable power consumption. Therefore it is a key enabling technology for future wireless ubiquity. Another aspect of flexibility is its ability to provide easy maintenance or upgrade of transceivers by adjusting through adequate parameters or software updates. Finally, flexibility is a must whenever cognitive radio is considered, since cognition relies on the ability of the transceiver to adapt its behaviour to decisions based on environment changes.

Description of work

Task TC.1: Flexible Multi-Processor System on Chip (MP-SOC) architectures

This task explores architectures for which algorithms are partitioned in concurrent processing tasks that are mapped onto a medium to large number of programmable processors, interconnected by means of a proper communication structure (e.g. Network on Chip – NoC). This solution offers high flexibility, but it is expected to introduce a larger cost overhead, in terms of area and dissipated energy.

MP-SOC are mainly based on three entities: the processing elements, the memory (would it be shared or distributed) and the communication networks. While multiprocessor architectures have been studied for several years, the on-chip implementation of MP-SOC architectures brings a number of new problems. For instance, compared to a typical communication networks, an MP-SOC is highly resource limited in terms of routing and power budget. TC1 does not aim at tackling all these challenges, but rather consider the most relevant when MP-SOC are applied to digital transceiver design. For instance, regarding the processing element, TC1 will analyse suitable ASIP architectures for communication algorithms and study how this approach can improve the architecture either in complexity or performance. Power consumption is also a crucial issue in the design of MP-SOP for transceiver application. TC1 will investigate architectural means to reduce power consumption through function profiling.

The communication structure ranges from simple bus architectures up to sophisticated NoC solutions; the choice of the communication structure may be a complex optimization problem, implying the exploration of a large design space, with several dimensions and parameters. However, the specificities of digital communication system implementation will be considered to adapt the complexity and topology of the on-chip communication scheme to the application requirements.

Another critical aspect in the study and implementation of MP-SOC definitely is the need for efficient design and simulation tools. Defining architecture and instruction set of the processing elements and designing the communication structure involve the exploration of several alternatives that need to be explored, functionally validated, characterized and compared in terms of cost and performance. Accurate models and efficient co-simulation environments are thus required to validate hardware and software components.

Main players: CEA-LETI, CNRS, CNIT

Task TC.2: Multi-standard processing for cognitive radio

It has been observed that more and more PHY standards are converging to different flavours of OFDM or OFDMA (e.g., IEEE802.11a/g, IEEE802.16.e, 3GPP LTE, DVB-T/H). Future multi-standard terminals will be requested to address these modes with minimal hardware complexity. Rather than considering an architecture able to implement “any” air interface, the scope of TC2 is to reduce the air interface investigation space to these relevant air interface by factorising their similarities in hardware. Restricting this set will result in “close” implementation if we consider distance being defined by the amount of changes at the hardware level to switch from one standard to the other. From this analysis we classify the hardware structures as modules that are common to several modes referred to as common factors that should be “installed” as hardware accelerators in the most efficient way and the features that are specific to a certain mode. This approach can be applied as well when single hardware functionality can be used in various functional blocks. The key driver for defining the boundary between common factors and specific logic will be hardware complexity, real-time operation and reconfiguration time. It is expected that several level of operator granularity will emerge for optimal hardware implementation. It is also expected that operator scheduling will differ from classical implementations.

To ease the use of such flexible heterogeneous architectures, an abstraction layer is needed as it enables to speed up the mapping of functionalities onto hardware platforms. Abstraction layer able to consider different targets will be investigated.

Main players: CEA-LETI, CNRS, UPC

Task TC.3: Flexible hardware architecture for computationally intensive processing

This task addresses specific algorithmic problems, aiming at proposing efficient processing architectures, with proper combination of cost, performance, flexibility and energy consumption. It then heavily involves the study and optimization of studied algorithms that have to be mapped to executing architectures according to defined optimum functions.

The focus here is on computationally intensive algorithms, which are expected to be critical from the complexity, throughput or energy perspectives. As a consequence, the required flexibility can hardly be achieved resorting to programmable processors or configurable FPGA devices; instead algorithms must be analyzed, evaluated and reformulated from the implementation point of view, in order to facilitate the mapping on a reduced number of parameterized processing elements, with few flexible interconnects.

Examples of algorithms that can benefit from this approach are from the channel decoder field (LDPC, turbo-codes), where the process of approaching the Shannon limit is continuously raising the level of complexity to be handled.

MIMO detection is an additional domain that today represents significant challenges in terms of implementation complexity. In the MIMO domain, detection techniques as sphere decoding have already been implemented in fully dedicated large integrated circuits, but the wide adoption of MIMO detection still needs architectures offering some elements of flexibility (e.g. support to multiple modulation schemes) at a limited cost. As MPSOC is a promising approach to tackle these algorithms, TC3 will work in close cooperation with TC1.

Main players: CNIT, CNRS